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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 19: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator (FBG Packages) (1)(2)
Speed Grade
Memory
Standard
I/O Bank Type
V CCAUX_IO (3)
-3
-2/-2L
1.0V
-1
-1M
0.9V
-2L
Units
4:1 Memory Controllers
DDR3
DDR3L
DDR2
HP
HR
HP
HR
HP
HR
N/A
N/A
N/A
N/A
N/A
N/A
1333
1066
1066
800
800
800
1066
800
800
800
800
667
800
800
667
667
800
667
800
800
667
N/A
667
533
800
800
667
667
800
667
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
RLDRAM III
HP
HR
N/A
N/A
550
500
450
N/A
350
450
MHz
2:1 Memory Controllers
DDR3
DDR3L
DDR2
QDR II+ (4)
RLDRAM II
LPDDR2
HP
HR
HP
HR
HP
HR
HP
HR
HP
HR
HP
HR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1066
1066
1066
800
800
800
550
450
533
667
667
1066
800
800
800
800
667
500
400
500
667
667
800
800
667
667
800
667
450
350
450
667
533
667
667
667
N/A
667
533
300
300
400
400
400
800
800
667
667
800
667
450
350
450
667
533
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
MHz
MHz
MHz
Mb/s
Mb/s
Notes:
1.
2.
3.
4.
V REF tracking is required. For more information, see the 7 Series FPGAs Memory Interface Solutions User Guide ( UG586 ).
When using the internal V REF , the maximum data rate is 800 Mb/s (400 MHz).
FBG packages do not have separate V CCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks.
The maximum QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations
are limited to 333 MHz for all speed grades and I/O bank types.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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